Integrated circuit (IC) fabrication can include a front-end-of-line (FEOL) process and a back-end-of-line (BEOL) process. The FEOL process is the first portion of IC fabrication where the individual devices, such as transistors, capacitors, and resistors, are patterned in the semiconductor. The FEOL process results in a wafer with isolated devices. Once the various devices have been created, the devices can be interconnected to form the desired electrical circuit. This occurs in a series of wafer processing steps referred to as BEOL process. The BEOL process is the second portion of IC fabrication where the individual devices get interconnected with wiring on the wafer. The BEOL process generally begins when the first layer of metal is deposited on the wafer. The BEOL process can include creating contacts, insulating layers, metal layers, and bonding sites for chip-to-package connections.
After the FEOL process has been completed, the individual devices may be subjected to a variety of tests to determine if the devices will function properly and reliably. ICs may be designed with testability features such as scan chains or built-in self-tests (BIST). Even with these testability features implemented in the IC, it may be difficult to exhaustively test each individual device of the FEOL portion of the IC for manufacturing defects and process variations.